This invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same, and more particularly to enhancement of the reliability of a gate insulating film of memory cells.
An EEPROM is a type of nonvolatile memory capable of electrically rewriting data and has a memory cell array in which memory cells for storing data are integrated. As the memory cell in the EEPROM, a MOSFET of a stacked gate structure having a floating gate and a control gate stacked is widely known.
FIG. 1A is a pattern plan view showing part of a memory cell array in which MOSFETs (memory cells) of the stacked gate structure are integrated, and FIG. 1B is a cross sectional view taken along the line 1B--1B of the pattern shown in FIG. 1A. As shown in FIGS. 1A and 1B, element isolation regions 102 are formed to separate active regions 104 from one another on the main surface of a p-type silicon substrate (or p-type well) 101. Under each of the insulating films 102, a P.sup.+ -type diffused layer 103 having higher impurity concentration than the substrate 101 is formed. The P.sup.+ -type diffused layer 103 is a channel stopper. On each of the active regions 104, a first thin gate insulating film 105 in which a tunnel current can flow is formed and a floating gate 106 is formed thereon. On each of the floating gates 106, a second gate insulating film 107 is formed and a control gate 108 is formed thereon. Thus, the gate of the memory cell is formed in the form of stacked gate structure in which the floating gate 106 and the control gate 108 are stacked. The floating gate 106 and the control gate 108 are formed by continuously effecting the etching process by use of the same mask and the edges of the stacked gate structures arranged on the row are aligned.
Source regions 109S and drain regions 109D are formed by ion-implanting n-type impurity into the active regions 104 by using the stacked gate structures and element isolation regions 102 as a mask. The end portion of the floating gate 106 is formed to extend on the element isolation region 102 and constructs a portion which is generally called a wing 110. The wing 110 functions to enlarge the opposed areas of the control gate 108 and the floating gate 106 so as to increase the capacitance between the control gate 108 and the floating gate 106.
An inter-level insulating film 150 is formed on the entire surface of the resultant semiconductor structure. On the inter-level insulating film 150, bit lines 151 are formed. The bit lines 151 are selectively connected to the drain regions 109D via bit line contact holes 152 formed in the inter-level insulating film 150. In FIG. 1A, only the positions of the bit line contact holes 152 are shown and the inter-level insulating film 150 and the bit lines 151 are omitted.
As the element isolation region 102 shown in FIGS. 1A and 1B, a LOCOS type film formed by thermally oxidizing a selected part of the main surface of the substrate 101 is widely used. In the LOCOS method, the main surface of the substrate 101 is thermally oxidized after a portion of the substrate 101 in which the active regions are formed is covered with an oxidation resistant film such as a silicon nitride film (Si.sub.3 N.sub.4). Since the silicon nitride film acts as a barrier against oxidation, a thick thermal oxidation film can locally be formed on a portion of the substrate 101 on which the element isolation regions are formed.
Recently, a trench element isolation method for forming trenches in a portion of the substrate 101 on which the element isolation regions are formed and filling insulator in the trenches becomes popular as the technique for making the dimensions of the element isolation region 102 smaller than the LOCOS type.
FIG. 2 is a cross sectional view showing part of a memory cell array in an EEPROM formed by use of the trench element isolation method. For example, the cross section of FIG. 2 corresponds to the portion taken along the line 1B--1B of FIG. 1A. In FIG. 2, portions which are the same as those of FIG. 1B are denoted by the same reference numerals. As shown in FIG. 2, in the trench type, trenches 111 are formed in a portion of the substrate 101 on which the element isolation regions are formed and the inner portion of the trench 111 is filled with insulator 112.
With the above trench type, since the element isolation region can be formed deeply into the substrate 101, the effective element isolation distance can be made larger than in the LOCOS type. Therefore, if the element isolation width is the same, the element isolation ability can be extremely enhanced in comparison with the LOCOS type.
Further, a self-aligned trench element isolation method capable of further reducing the isolation distance in the row direction in comparison with the trench type for element isolation in the memory cell array of the EEPROM is also known. The self-aligned trench element isolation method is disclosed in IEDM 94 pp. 61-64 "A 0.67 .mu.m.sup.2 SELF-ALIGNED SHALLOW TRENCH ISOLATION CELL (SA-STI (CELL) FOR 3V-only 256 Mbit NAND EEPROMs" S. Aritome et al., for example.
FIG. 3 is a cross sectional view showing part of a memory cell array in the EEPROM formed by use of the self-aligned trench element isolation method. The cross section shown in FIG. 3 corresponds to the portion taken along the line 1B--1B of FIG. 1A, for example. In FIG. 3, portions which are the same as those of FIG. 1B are denoted by the same reference numerals. As shown in FIG. 3, in the self-aligned trench type, wings 110 are formed in a direction perpendicular to the substrate 101 on the boundaries between active regions 104 and trenches 111. Therefore, the integration density can be enhanced in comparison with the LOCOS type and trench type in which the wing 110 is enlarged in the row direction.
FIG. 4 is a block diagram showing the basic construction of a conventional EEPROM. In FIG. 4, only a typical circuit block which lies around a memory cell array section 201 is extracted and shown. Generally, the EEPROM contains the memory cell array section 201 for storing data and a peripheral driving circuit section 202 for driving the array section 201 and activating the storage function thereof. The circuit section 202 includes a row decoder section 301, sense amplifier circuit section 302, column decoder section 303 and booster circuit section 304. The row-decoder section 301 is connected to word lines WL in the memory cell array section 201 to selectively activate the word line WL. The sense amplifier circuit section 302 is connected to bit lines BL in the memory cell array section 201 and amplifies and latches read data from a memory cell MC or program data into the memory cell MC. The column decoder section 303 is connected to the bit lines BL in the sense amplifier circuit section 302 to selectively activate the bit line BL. The booster circuit section 304 raises a given voltage to create a desired internal voltage and supplies the same to the row decoder section 301, for example.
For element isolation of the array section 201 and circuit section 202, one of the above three element isolation techniques can be used or different element isolation techniques can be used for them. Particularly, in the array section 201 which requires miniaturization, the trench element isolation or self-aligned trench element isolation becomes extremely effective if the minimum dimension becomes 0.4 .mu.m or less. In contrast, in the circuit section 202, the element isolation distance and transistors are larger than in the array section 201. This is because a program voltage (for example, 20V) is applied to the PN junction and the contact area and gate length are larger than in the memory cell MC due to the structure of the transistor, for example. Because of the process margin and integration, the LOCOS element isolation which can be a more stably established technique than the trench element isolation may be suitably used in the circuit section 202 in some cases. In such a case, the trench element isolation or self-aligned trench element isolation is used in the array section 201 and the LOCOS element isolation is used in the circuit section 202.
FIG. 5 is a circuit diagram showing the array section 201 and peripheral driving circuit section 202 in the NAND type EEPROM, and more particularly, the connecting portion with the row decoder section 301 in a simplified form. As shown in FIG. 5, each of the word lines WL (WL1 to WLn) and selection gate lines SG (SG1, SG2) is connected to a corresponding one of high breakdown voltage transistors HVTr contained in the row decoder section 301. In the program mode, a voltage equal to or higher than "the program voltage+the threshold voltage of the transistor HVTr" is applied to the gate of the transistor HVTr to turn ON the transistor HVTr. As a result, the program voltage (for example, 20V) is transferred to the word line selected for programming via the drain-source path of the transistor HVTr. In FIG. 5, the positions of contact holes 153, 155 are shown in the circuit diagram as equivalent positions. The source region of the transistor HVTr is connected to the word line WL or the source region thereof is connected to the selection gate line SG by means of a metal wiring 154 via the contact holes 153, 155.
FIG. 6 is a cross sectional view of part of the circuit shown in FIG. 5. In FIG. 6, the LOCOS element isolation is used for both of the array section 201 and the row decoder section 301 or circuit section 202. As shown in FIG. 6, the control gate 108 is formed to extend from the upper portion of the active region 104 in the array section 201 to the upper portion of the element isolation insulating film 102 in the peripheral driving circuit section 202. In this portion, the control gate 108 is connected to the metal wiring 154 via the contact hole 153 and connected to the transistor HVTr in the row decoder section 301 shown in FIG. 5.
The element isolation region 102 in the array section 201 is formed of a thin line pattern extending in a direction crossing the control gate (word line) 108 and repeated with periodicity. In contrast, in the element isolation region 102 in the circuit section 202, there is no periodicity in which the thin line pattern is repeated. For this reason, the periodicity of the pattern is disturbed on the element isolation region 102 corresponding to the boundary between the array section 201 and the circuit section 202. This makes it difficult to process the floating gates 106 with the same dimension in the outermost portion of the array section 201 and in the internal portion thereof at the time of lithography, for example. In order to eliminate the disturbance of the periodicity, for example, several dummy patterns are formed in the outermost portion of the array section 201. However, since the outermost portion of the array section 201 is formed in contact with the element isolation region 102 of the circuit section 202, the pattern of the floating gate 106 becomes different from the pattern of the floating gate 106 lying inside the array section 201 as shown in FIG. 6.
As described above, the pattern of the floating gate 106 in the outermost portion is different from the pattern of the floating gate inside the memory cell array section 201. For this reason, the capacitance between the floating gate 106 and the control gate 108 is different for a cell in the dummy pattern lying in the outermost portion and for a cell in the normal pattern lying inside the above cell and actually used as a cell.
FIG. 7A is an equivalent circuit diagram of a memory cell in the EEPROM and FIG. 7B is a perspective view for illustrating the dimensions of a dummy pattern cell and the dimensions of a normal cell (which is hereinafter referred to as a memory cell). As shown in FIG. 7A, the memory cell can be replaced by a circuit having capacitors C1 and C2 serially connected between the substrate 101 and the control gate 108. The electrode which is commonly used by the capacitors C1 and C2 corresponds to the floating gate 106. In the above equivalent circuit, the capacitor C1 is a capacitor between the substrate 101 and the floating gate 106 and the capacitor C2 is a capacitor between the floating gate 106 and the control gate 108. Further, the dielectric of the capacitor C1 is the first gate insulating film 105 between the substrate 101 and the floating gate 106 and the dielectric of the capacitor C2 is the second gate insulating film 107 between the floating gate 106 and the control gate 108.
When a potential VCG is applied to the control gate 108 shown in FIG. 7A, a potential VFG of the floating gate 106 is expressed by the following equation (1). ##EQU1##
When the film thickness of the dielectric of the capacitor C1 is T, the electric field E applied to the dielectric is expressed by the following equation (2). ##EQU2##
It is understood from the equation (1) that the potentials VFG of the floating gates 106 of the dummy pattern cell and the memory cell are different from each other if the capacitances C2 are different when the same potential VCG is applied to the control gates 108 of the dummy pattern cell and the memory cell.
Further, it is understood from the equation (2) that the electric fields applied to the dielectrics of the capacitors C1, that is, the first gate insulating films 105 are different from each other if the potential of the floating gate 106 of the dummy pattern cell and the potential of the floating gate 106 of the memory cell are different from each other.
This is more specifically explained with reference to FIG. 7B. In FIG. 7B, Wd, Wc are the widths of the active regions 104 of the dummy pattern cell and the memory cell, Ww is the width of the wing 110, l indicates the length of extension of the floating gate 106 on the element isolation region 102 in the peripheral driving circuit section 202, and L indicates the channel length of the dummy pattern cell and memory cell.
The dielectric constants of the first gate insulating film 105 and second gate insulating film 107 are respectively set to .epsilon.1 and .epsilon.2, the film thicknesses of the first gate insulating films 105 of the dummy pattern cell and the memory cell are respectively set to Td and Tc, and the film thicknesses of the second gate insulating films 107 of the dummy pattern cell and the memory cell are set to T2. Further, .epsilon.0 is the dielectric constant of vacuum.
In the thus set condition, the capacitance C1 of the memory cell is expressed by the following equation (3). ##EQU3##
The capacitance C2 of the memory cell is expressed by the following equation (4). ##EQU4##
From the equations (1), (3) and (4), the potential VFG of the floating gate 106 of the memory cell when the potential VCG is applied to the control gate 108 is expressed by the following equation (5). ##EQU5##
Further, the capacitance C1 of the dummy pattern cell is expressed as follows. ##EQU6##
The capacitance C2 of the dummy pattern cell is expressed as follows. ##EQU7##
From the equations (1), (6) and (7), the potential VFG of the floating gate 106 of the dummy pattern cell when the potential VCG is applied to the control gate 108 is expressed by the following equation (8). ##EQU8##
Further, from the equations (2) and (5), the electric field Ec applied to the first gate insulating film 105 of the memory cell is expressed by the following equation (9). ##EQU9##
Further, from the equations (2) and (8), the electric field Ed applied to the first gate insulating film 105 of the dummy pattern cell is expressed by the following equation (10). ##EQU10##
It is understood from the equations (9) and (10) that the electric field Ed applied to the first gate insulating film 105 in the dummy pattern cell may be different from the electric field Ec in the memory cell in some cases.
That is, if a portion of the floating gate 106 of the dummy pattern cell which extends on the element isolation region 102 in the circuit section 102 is wide, the degree of coupling between the control gate 108 and the floating gate 106 of the dummy pattern cell becomes high and the electric field Ed becomes stronger than the electric field Ec. In contrast, if the extending portion is narrow, the electric field applied to the second gate insulating film 107 becomes stronger as the electric field Ed becomes weaker.
From the equations (9) and (10), the ratio of the electric field Ed to the electric field Ec is expressed by the following equation (11). ##EQU11##
From the equation (11), it is understood that the dummy pattern cell and the memory cell may be formed with the same dimensions in order to set the electric fields Ed and Ec to the same value. However, as described above, it is difficult to form the pattern in the outermost portion and the inner pattern with the same dimensions under circumstances of lithography, and the dimensions of the floating gate 106 of the dummy pattern cell will be larger than the floating gate 106 of the memory cell.
The first gate insulating film 105 is a portion via which electrons pass at the time of programming and erasing and the film thickness thereof is set to an optimum value according to the memory cell. Therefore, in the first gate insulating film 105 of the dummy pattern cell to which the electric field Ed higher than the electric field Ec is applied, the reliability with respect to the withstand voltage, for example, is lowered in comparison with the first gate insulating film 105 of the memory cell. If the insulating characteristic of the first gate insulating film 105 of the dummy pattern cell is lowered, the electric field applied to the second gate insulating film 107 becomes larger and the insulating characteristic of the second gate insulating film 107 starts to be lowered. In due course of time, the insulating characteristics of both of the first gate insulating film 105 and second gate insulating film 107 are deteriorated and the insulating property between the control gate and the substrate 101 will be lost. As a result, a phenomenon which deteriorates the characteristic of the memory cell occurs and, for example, the potential of the control gate 108 will not be raised to a sufficiently high level. Further, if dielectric breakdown occurs in the second gate insulating film 107 at the time of application of a high voltage for programming, for example, the first gate insulating film is also destroyed and the memory cell becomes defective.
Such a problem caused by a difference in the pattern of the floating gate 106 in the outermost portion will occur even if the trench isolation is used for both of the array section 201 and the circuit section 202 as shown in FIG. 8 or even if the trench element isolation is used for the array section 201 and the LOCOS element isolation is used for the peripheral driving circuit section 202 as shown in FIG. 9.
Further, in a case where the self-aligned trench element isolation is used for both of the array section 201 and the peripheral driving circuit section 202 as shown in FIG. 10, the capacitance C2 of the outermost dummy pattern cell becomes smaller than the capacitance C2 of the memory cell. For this reason, the electric field applied to the second gate insulating film 107 of the dummy pattern cell becomes stronger to lower the insulating characteristic of the second gate insulating film 107, and consequently, the electric field applied to the first gate insulating film 105 becomes stronger to lower the insulating characteristic of the first gate insulating film 105. As a result, like the above-described case, the characteristic of the memory cell is deteriorated and the memory cell becomes defective.
Further, in a case where the self-aligned trench element isolation is used for the array section 201 and the LOCOS element isolation is used for the peripheral driving circuit section 202 as shown in FIG. 11, the capacitance C2 of the outermost dummy pattern cell becomes larger than the capacitance C2 of the memory cell so that the insulating characteristic of the first gate insulating film 105 will be lowered, and consequently, the electric field applied to the second gate insulating film 107 will become stronger to lower the insulating characteristic of the second gate insulating film 107 and thus the characteristic of the memory cell is deteriorated.
As described above, in the conventional nonvolatile semiconductor memory device, since the pattern of the cells in the outermost portion of the memory cell array section and the pattern of the cells lying inside the above pattern are different from each other, the insulating characteristic between the control gate and the substrate is deteriorated, and as a result, there occurs a problem that the characteristic of the memory cell is deteriorated and the memory cell becomes defective.